Back Gate Bias Stressing on Extremely Thin SOI (ETSOI) MOSFETs with Gate Last Process Integration

Abstract

In this paper, ETSOI transistors fabricated with gate last process scheme with thin channel layers of 4 to 11nm are provided with superior device performance. For a given gate length less than 30nm, DIBL and Swing are achieved with 48mV/V and 65mV/Dec respectively with stressing of back gate bias. Threshold voltage can be tuned within range of 0.8 volts (Vdd=-0.05v). It is large enough for adjusting device performance. Back gate bias stressing would enhance carrier confinement to top gate while large electrical field is induced in the ultra-thin channel layer which would impact on the performance of DIBL. Also, from our results, it is shown that device with thicker channel layer of 11nm are more sensitive to back gate bias comparing with that with thinner channel layer of 4nm.