AlGaN/AlN/SiC Metal-Oxide-Semiconductor Heterostructure Field-Effect Transistors with Al2O3 Gate-Oxide and Step-Graded AlGaN Channel

Abstract

Al0.75Ga0.25N/n-AlxGa1-xN/Al0.75Ga0.25N/AlN metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs), grown on a SiC substrate, with step-graded Si-doped (n = 3 × 1018 cm-3) widegap AlxGa1-xN channel and Al2O3 gate-dielectric are investigated. Increased Al-compositions with x = 0.25, 0.5, and 0.75 towards the buffer were devised in the composite widegap channel. The high-k Al2O3 dielectric/passivation layer was grown by using a non-vacuum ultrasonic spray pyrolysis deposition (USPD) method. Experimental comparisons were made with respect to a conventional Schottky-gate HFET. The epitaxial structure of the studied Al2O3-dielectric Al0.75Ga0.25N/n-AlxGa1-xN/Al0.75Ga0.25N/AlN MOS-HFET (sample A) and Schottky-gate HFET (sample B). Both devices have the identical epitaxial structure grown on a SiC substrate by using a low-pressure metal-organic chemical vapor deposition (LP-MOCVD) system. The layer structure includes an undoped AlN buffer, a 20-nm undoped Al0.75Ga0.25N barrier, a 150-nm step-graded Si-doped (n = 3 × 1018 cm-3) AlxGa1-xN channel (x = 0.25, 0.5, and 0.75), and a 20-nm undoped Al0.75Ga0.25N barrier. Standard photolithography and lift-off techniques were used for device processing. For sample B, mesa etching was performed with respect to a 100-nm thick Ni barrier by using an inductively coupled-plasma reactive ion etcher (ICP-RIE). Flow rates were tuned and set at 10 sccm and 20 sccm for the mixed etching gases of BCl3 and Cl2, respectively. The 20-nm undoped Al0.75Ga0.25N barrier was etched away before deposition of source/drain electrodes. Ti (10 nm)/Al (50 nm)/Ni (10 nm)/Au (50 nm) were evaporated. The source/drain ohmic contacts were formed by annealing the sample for 25 seconds at 900°C by using a rapid thermal annealing (RTA) system (ULVAC MILA-5000). Then, 30-nm thick Al2O3 layer was deposited on the Al0.75Ga0.25N barrier by using the USPD technique. Finally, gate electrode of Ni (100 nm)/Au (50 nm) was evaporated after gate photolithography. As for sample A, the gate electrode was formed directly on the surface of Al0.75Ga0.25N barrier without oxide deposition. Improved device performance of the present MOS-HFET design have been obtained, including maximum drain-source current density (IDS, max ) of 130.1 A/mm at VGS = 10 V and VDS = 20 V, IDS at VGS = 0 V (IDSS0 ) of 83.1 mA/mm, on/off-current ratio (Ion /Ioff ) of 1.4 × 107, maximum extrinsic transconductance (gm, max ) of 11.8 mS/mm, two-terminal off-state gate-drain breakdown voltage (BVGD ) of -404 V, and three-terminal on-state drain-source breakdown voltage (BVDS ) of 364 V at 300 K. The present MOS-HFET design has also shown high spectral responsivity (SR) of 737 A/W under 250-nm deep-UV radiation at 300 K.