(Invited) Non Quasi Static Modeling of Printed Organic Thin Film Transistors in Large Signal and Small Signal Operation

Abstract

As one of the main expected advantages of organic electronics is the low cost, printing technologies are actively investigated for the fabrication of OTFTs. Techniques such as ink-jet or gravure printing frequently results in organic semiconductor (OSC) layers with low crystallinity and relatively low carrier mobility. Moreover, the minimal feature sizes attainable are often in the range of the tens of microns. Hence, the resulting carrier transit time (τ) in the channel of OTFTs can be of the order of tenth of milliseconds with associated cut off frequencies in AC regime in the range of few kilohertz [1]. Due to the large tolerances associated to printing processes, the layout of printed OTFTs often includes semiconductor regions whose dimensions are chosen prudently larger than the spacing existing between the source and drain contacts. The presence of the parasitic regions, that is negligible in DC operation, must be accounted in order to accurately reproduce the dynamic operation of these devices. Due to the relatively high value of τ, it is very likely that in practical applications organic circuits are operated with signals varying on a time scale of the same order or shorter than τ. Hence, the carriers in the device don’t have enough time to reach the distribution associated to stationary conditions and the OTFTs enter in non quasi static (NQS) regime of operation. The device response to large variation of its polarization (large signal, LS) becomes dependent on the delay times associated with the high value of τ. Moreover, in NQS regime the device effective admittance in small signal (SS) AC operation is found to be dependent upon the small signal frequency [2][3]. Hence, to successfully design electrical circuits employing printed OTFTs, it is necessary to develop compact models that are able to precisely reproduce not only the DC operation but also the LS and SS AC behavior of these devices. In this work, a large signal non quasi static (LS-NQS) compact model has been developed: the model is based on the current continuity equation that, in the case of a MOSFET transistor channel, can be cast as a partial differential equation (PDE) governing the carrier density distribution during time, Q(x,t), in a distributed RC transmission line. In order to solve this PDE, the space variable x is discretized by using a spline collocation approach: the PDE is transformed in a set of ordinary differential equations (ODE) in the time variable t, that can be solved numerically in a “SPICE-like” circuit simulation environment [4], [5]. The spline collocation approach allows to choose the number of splines (N) in which the device channels and the parasitic regions are split: by choosing an appropriate value for N it is possible to find the best compromise between computation accuracy and performance. NQS models have been already investigated and developed for crystalline silicon MOSFETs. The model presented in this work differs from the crystalline silicon counterparts in two major aspects: 1 – the equations accounting for the charge and current densities are based upon the variable range hopping (VRH) theory that is well suited for amorphous organic semiconductors[6]. 2 – the model takes into account the presence of parasitic regions by imposing appropriate boundary conditions on their extremities. The LS-NQS model has been implemented in Verilog-A and validated by simulating the electrical behavior of multi-fingered OTFTs, with staggered top-gate configuration, fabricated on PEN substrates by means of a fully printed process. The devices were characterized and simulated in DC, and SS AC operation. A common source amplifier circuit has been realized and measured in LS operation. As can be seen from fig. 1, the model reproduce perfectly the device behavior in LS operation. Moreover, the use of the model has permitted to gain several physical insights concerning the device operation. [1] J. S. Chang et al., IEEE J. Emerg. Sel. Top. Circuits Syst., vol. 7, no. 1, pp. 7–26, Mar. 2017, doi: 10.1109/JETCAS.2017.2673863. [2] A. Valletta et al., IEEE Trans. Electron Devices, vol. 61, no. 12, pp. 4120–4127, Dec. 2014, doi: 10.1109/TED.2014.2364451. [3] J. Leise et al., IEEE Trans. Electron Devices, vol. 67, no. 11, pp. 4672–4676, Nov. 2020, doi: 10.1109/TED.2020.3018094 [4] A. Valletta et al. in 2016 46th European Solid-State Device Research Conference (ESSDERC), Lausanne, Switzerland, Sep. 2016, pp. 460–463, doi: 10.1109/ESSDERC.2016.7599685. [5] A. Valletta et al. in 2017 European Conference on Circuit Theory and Design (ECCTD), Catania, Sep. 2017, pp. 1–4, doi: 10.1109/ECCTD.2017.8093225. [6] F. Torricelli et al., IEEE Trans. Electron Devices, vol. 56, no. 1, pp. 20–30, Jan. 2009, doi: 10.1109/TED.2008.2007717. Figure 1