(Invited) Advanced Modeling for Full-Chip Low-k1 Lithography Simulations

Abstract

Full-chip computational lithography is an important technology that enables low-k1 patterning. Examples of its applications include optical proximity correction (OPC), source-mask optimization (SMO) and verifications. In these applications, lithography models are required to predict the printed patterns on the wafer. Therefore the model accuracy has a direct impact to the quality of the final result. Rigorous physical models are accurate but computationally expensive. Therefore simple approximate models are generally used in full-chip applications. As the k1-factor continues to shrink, the errors produced by these simple models become unacceptable. Advanced models with improved accuracy and reasonable speed are required for low-k1 applications. In this work we will discuss the issues with the existing full-chip models and the development of advanced models.