Reduction of Hot Carrier Effects in Silicon-on-Glass TFTs

Abstract

Hot carrier (HC) instability of thin-film transistors (TFTs) fabricated on single-crystal,silicon-on-glass (SiOG) substrates is studied. The formation of the SiOG substrate is achieved by the transfer of a single-crystal silicon film to a display-glass substrate. The transfer process creates an in-situ barrier layer free of mobile ions in the glass adjacent the silicon film. The n- and p-channel TFT transfer characteristics typically exhibit excellent on-state performance with gate voltage swing values of 180 mV/decade, electron and hole mobilities of ∼ 251 and 201 cm2/V·s respectively, and threshold voltages of approximately −0.3 and −1.2 V for the n- and p-channel TFT’s respectively. While p-channel TFTs exhibit good stability, on-current degradation is observed in the transfer characteristics of the n-channel TFT. The degradation is due to HC stress. In this study, the integration of a lightly doped drain (LDD) structure in the n-channel SiOG TFTs to minimize HC instability is reported. The LDD design incorporates 2 μm offset regions. The offset regions are lightly doped (n-) with phosphorus ions implanted at 10 keV. N-levels of ∼ 1 × 1013, 2 × 1013, and 3 × 1013 cm−2 are analyzed to determine the optimum doping conditions that reduce HC instability while minimizing degradation in the on-state device performance.