Advanced Strained-Silicon and Core-Shell Si/Si1-xGex Nanowires for CMOS Transport Enhancement

Abstract

Top-down fabrication and characterization of vertically-stacked suspended strained-silicon nanowires (s-SiNWs) and Ge-shell/Si-core NWs are demonstrated. Epitaxially-grown strained-Si/relaxed-Si0.7Ge0.3 superlattice structures with up to 5 periods were patterned into arrays of nanoscale wires, and s-SiNWs were suspended by selective etching of the inter-level Si0.7Ge0.3 layers. Micro-Raman measurements reveal that 2.3GPa of tensile stress (mainly uniaxial) is present at the midpoint of 30 nm-wide s-SiNWs, and this amount of stress is maintained in 5-level-stacked nanowires. In addition, p-MOSFETs with Si-core/Ge-shell nanowire channels formed by selective epitaxial growth of Ge on the Si-nanowires were realized and integrated with a high-K/metal gate process to investigate hole transport in these non-planar nano-heterostructures. It is observed that defects in the Ge originate from the Si corners. In addition, Ge {111} facets are seen. Hole mobility increase, as high as 40%, has been observed as the NW width is decreased down to 20 nm.