Process Simulation and Experimental Study of Stress Memorization in Strained Silicon nMOSFETs

Abstract

Results from process simulations of the stress memorization technique (SMT) for nanoscale n-channel metal-oxide-semiconductor field effect transistors (nMOSFETs) are presented. Spatial distribution of stress components within the device were computed for different germanium dose in the pre-amorphization implant (PAI) step, different peak anneal temperatures in spike annealing and different tensile stress of the capping layer. During the spike anneal, stress is enhanced in the dielectric spacer due to viscoelastic relaxation of the capping layer. The stress induced in the channel by the spacer and the polysilicon gate after capping layer etch is non-uniform with maxima near the gate edges. Electrical measurements of fabricated SMT nMOSFETs are consistent with the simulation results.