III-V MOSFETs: Surface Passivation, Source/Drain and Channel Strain Engineering, Self-Aligned Contact Metallization
-
Published:2011-04-25
Issue:3
Volume:35
Page:351-361
-
ISSN:1938-5862
-
Container-title:ECS Transactions
-
language:
-
Short-container-title:ECS Trans.
Author:
Yeo Yee-Chia,Chin Hock-Chun,Gong Xiao,Guo Huaxin,Zhang Xingui
Abstract
In this paper, we discuss the research and development of gate-stack, source/drain, and contact process modules for high-mobility III-V n-MOSFETs. Work performed in our research group will be reviewed. Surface passivation technologies were developed for forming gate stacks on III-V materials such as GaAs and InGaAs. In situ doped lattice-mismatched source/drain (S/D) stressors were integrated in InGaAs MOSFETs with for reduction of S/D series resistance as well as for channel strain engineering. High-stress liner stressor was also used for inducing strain in the channel of InGaAs FETs. Several salicide-like process technologies were developed for self-aligned contact metallization in III-V MOSFETs. A III-V multiple-gate transistor with lightly doped fin with retrograde doping for suppression of short channel effects was demonstrated.
Publisher
The Electrochemical Society
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献