Effect of the Dummy Gate on the Capacitance Characteristics of the LDMOSFETs

Abstract

In this article the impact of geometrical parameters of the dummy gate on capacitance characteristics for RF-LDMOS transistors is analyzed and studied by using a 2-D numerical TCAD process and device simulator. Firstly, the device structure and fabrication process are described. Then measured and simulated capacitance characteristics of the fabricated RF-LDMOS transistors are compared, confirming the effectiveness of the TCAD simulations. On the basis of this, further extensive simulations on the device capacitance characteristics for varying thickness of the oxide layer under and beside the dummy gate (tfox) and length of the dummy gate over n-drift region (Lf) are carried out. Based on these simulation results, the effects of the dummy gate on various capacitance components are analyzed and discussed, indicating that feedback capacitances can be effectively reduced by the introduction of the dummy gate to the device, nevertheless, at the expense of increased output and input capacitances. For this reason, the key geometry parameters of the dummy gate have to be traded off in order to optimize device design.