Promised Design of Energy-Efficient Negative-Capacitance Vertical Tunneling FET
Author:
Funder
Ministry of Science and Technology, Taiwan
Publisher
The Electrochemical Society
Subject
Electronic, Optical and Magnetic Materials
Link
https://iopscience.iop.org/article/10.1149/2162-8777/ac10b4/pdf
Reference30 articles.
1. Low-voltage tunnel transistors for beyond CMOS logic;Seabaugh;Proc. IEEE,2010
2. Novel SiGe/Si line tunneling TFET with high Ion at low VDD and constant SS;Blaeser,2015
3. A high-performance InAs/GaSb core–shell nanowire line-tunneling TFET: an atomistic mode-space NEGF study;Afzalian;IEEE J. Electron Devices Soc.,2019
4. Simulation of GeSn/Ge tunneling field-effect transistors for complementary logic applications;Liu;Appl. Phys. Express,2016
5. Negative capacitance for boosting tunnel FET performance;Kobayashi;IEEE Trans. Nanotechnol.,2017
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