A Physics-Based Chip-Scale Surface Profile Model for Tungsten Chemical Mechanical Planarization

Abstract

In this work, a new physics-based chip-scale surface profile model is proposed to focus on investigating the influence of the design pattern effects on the tungsten surface topography in the chemical mechanical planarization (CMP) process. Due to its significance of the contact pressure on CMP planarity simulation, a two-scale contact pressure computation method is constructed to obtain an accurate pressure distribution between the wafer surface and the polishing pad. First, chip-scale contact mechanics-based global pressure has been introduced to capture the long range height variation of W CMP caused by deposition and polishing processes. Then feature-scale pattern dependent effect is considered to accurately calculate the local contact pressure in constructing the final removal rate formula and achieving chip surface profile simulation. The calculated local contact pressure is further integrated with the fundamental of steady-state oxidation reaction to construct a new material removal rate model, which systematically captures the effects of mechanical abrasion and concentration of chemical reagent on the polishing rate. The model prediction results are consistent with the collected experimental data in predicting the dishing effect at different slurry conditions. The simulated surface topography and polishing removal rate characteristics post tungsten CMP indicate prominent design pattern-dependent effects. Therefore, the present W CMP model can be utilized to assist in analyzing the influence of the design pattern effects on the wafer surface topography and performing sensitivity analysis of design parameters on the surface planarity. It can also be readily incorporated into a design for manufacturability flow to form a chip-scale planarity simulator to detect the hotspots of the entire design layout.