Using Hetro-Structure Window in Nano Scale Junctionless SOI MOSFET for High Electrical Performance

Abstract

A new junctionless MOS transistor is proposed in this paper using hetro-structure technology. A T-shape SiGe is applied under the source and channel region to extend the depletion region in the device. The Si(1−x)Gex region with a mole fraction of x = 0.3 for the germanium, changes the surface potential of the device due to the different band gap than silicon. Off-current in the proposed SiGe region in buried oxide of Junctionless SOI-MOSFET (SG-JLMOS) reduces significantly as it is compared to the Conventional Junctionless SOI-MOSFET (C-JLMOS). Also, using a window with higher thermal capability than silicon dioxide reduces maximum lattice temperature in the active region. In this situation, the reliability of the device increases and the better performance of the transistor is achieved in high temperature. Our simulation with 2D ATLAS simulator shows that DIBL and subthreshold swing have lower values in the proposed SG-JLMOS. So, short channel effects which are the vital parameters in the nano scale device are controlled, considerably.