Abstract
The effect of ceria abrasive compound with zirconia and silica on polishing performance of SiO2 dielectric was studied. The results show that adding zirconia and silica to the ceria slurry can improve the polishing performance of SiO2 dielectric. When the mass ratio of ceria and zirconia is 4:3, the material removal rate (MRR) of SiO2 dielectric is increased to 218.6 nm min−1 at pH 3. Meanwhile, under the same pH, when the ratio of ceria to silica is 2:1, the MRR of SiO2 dielectric is 228.8 nm min−1. But the MRR reaches the highest at pH 5, the MRR of SiO2 dielectric reached 477.7 nm min−1 after the combination of ceria and zirconia, and 538.2 nm min−1 after the composite of ceria and silica. With the increase of the average particle size of silica, the MRR of SiO2 dielectric increases gradually. When the silica particle size is 80 nm, the MRR of SiO2 dielectric is the highest of 538.2 nm min−1. When using PL-3 instead of alkaline silica to verify the polishing rate of TEOS dielectric and Si3N4, the removal rate of TEOS dielectric reached 1080.6 nm min−1, the removal rate of Si3N4 was only 91.9 nm min−1, and the removal rate selectivity was 11.75:1. At the same time, the surface roughness of SiO2 dielectric is also decreased after the abrasive mixture.
Funder
One Hundred Talent Project of Hebei Province of China
Publisher
The Electrochemical Society
Subject
Electronic, Optical and Magnetic Materials
Reference18 articles.
1. 0.67 μm2 self-aligned shallow trench isolation cell (SA-STI cell) for 3 V-only 256 Mbit NAND EEPROMs;Aritome;International Electron Devices Meeting,1994
2. A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme;Suh;International Solid-State Circuits Conference,1995
3. A 117-mm2 3.3-V only 128-Mb multilevel NAND flash memory for mass storage applications;Jung;International Solid-State Circuits Conference,1996
4. A novel isolation-scaling technology for NAND EEPROMs with the minimized program disturbance;Satoh;International Electron Devices Meeting,1997
5. A negative V/sub th/ cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories;Takeuchi;Journal of Solid-State Circuits,1999
Cited by
3 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献