Noise Effects in the Design of Digital Circuits Based on CNTFET

Abstract

In this paper initially we present two CNTFET models: the first, already proposed by us and the second the Stanford model, recalling our method to match the output characteristics and transconductance characteristics between these two models. Then we briefly recall a compact noise model, proposed by us, used to simulate the performance of some digital CNTFET circuits, for which we present the DC, transient and noise analysis. In particular we examine a inverter gate and the proposed analysis allows to determine the optimal value of input voltage which makes the noise effects negligible.