Author:
Maeda Tatsuro,Mieda Eiko,Ishii Hiroyuki,Itatani Taro,Hattori H,Yasuda Tetsuji,Maeda Atsuhiko,Kurashima Yuichi,Takagi Hideki,Aoki T,Yamamoto T,Ichikawa Osamu,Osada T,Takada T,Hata Masahiko,Yugami J,Ogawa A,Kikuchi T,Kunii Y
Abstract
We have realized patterned Ge-on-Insulator wafers by large-scale layer transfer technology. In conjunction with low-temperature bonding and patterned Epitaxial Lift-Off (ELO) technique, high quality Ge or III-V layer transfer was achieved in full-wafer scale. Furthermore, to expand the transferred area, multiple chip-to-wafer bonding and thin epitaxial film transfer has been demonstrated on 300 mm Si wafer. Low temperature layer transfer technology using ELO technique provide the flexible opportunity to elaborate Ge and III-V based substrates for post silicon CMOS as well as for monolithic heterogeneous integration in a cost effective manufacturing.
Publisher
The Electrochemical Society
Cited by
6 articles.
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