Erasing Characteristics of Stacked-Gate Flash Memories with High-k Dielectrics

Abstract

By 2-D MEDICI simulation, flash memories with high-k IPDs clearly exhibit significant improvement in SFN erasing speed over those with conventional ONO IPD. Choosing HfO2 as the IPD, erasing voltage can be reduced larger than 48% at a typical 0.1ms erasing time due to significantly improved gate coupling ratio. However, effects of high-k TDs on erase performance of the stacked-gate flash memories with fixed HfO2 IPD is quite contrary with respect to the improvement observed for the flash memory with high-k IPDs. Due to reduced gate coupling ratio, erasing speed of the stacked-gate flash memories with high-k TDs using SFN tunneling is helpless. Compared to the flash memory with HfO2 IPD and SiO2 TD, erasing voltage for the flash memory with both HfO2 IPD and TD will degrade erasing voltage larger than 41% at a 0.1ms erasing time. On the other hand, increased electric field on HfO2 IPD would produce excess charge loss and narrow the operation window between programmed and erased state.