(Invited) Integration Challenges of III-V Materials in Advanced CMOS Logic

Abstract

The superior transport properties of III-V materials make them attractive choices to enable improved performance at low power. This paper examines the integration challenges of III-V materials in advanced CMOS logic at or beyond the 11 nm technology node, and reports VLSI compatible junction, contact and gate stack process modules with Xj¬<10nm, ND>5x1019cm-3, ρc= 6 Ω.µm2 and Dit = 4 x 1012 eV-1.cm-2.