Carrier Mobility Variations in Self-Aligned Germanium MOS Transistors

Abstract

Tungsten gate germanium MOS transistors have been manufactured on bulk germanium platforms. Hole mobility in the range 450 cm2/Vs has been achieved on bulk germanium, but mobility is reduced during the densification of thinner dielectrics at 600C. This may be due to the formation of volatile GeO at the interface during densification. Low temperature measurements of the thinner dielectric device indicate that lattice scattering is dominant at room temperature for the device where the densification was omitted and the excellent subthreshold slopes at low temperatures also indicate devices of good quality.