Growth and Processing Defects in CMOS Homo- and Hetero-Epitaxy

Abstract

The impact of different processing steps on the electrical properties of homo- and hetero-epitaxial junctions deposited on silicon substrates is described. In particular, the influence of the pre-epi in situ cleaning, using a high temperature bake in H2 is investigated. It is shown that the removal of oxygen and carbon from the starting surface is crucial in obtaining high-quality, low-leakage epitaxial junctions. In addition, it is demonstrated that post-epi implantation and anneal should be carefully optimized in order to maintain the strain in SiGe layers and to control the defect formation.