Fabrication of Silicon Nanopore Arrays with Three-Step Wet Etching

Abstract

Solid-state nanopore arrays are realized with a well-controlled, three-step, anisotropic wet etching process with different KOH bath temperatures. The influence of etchant concentration and temperature on the etching rate is investigated. Nanopore arrays with an average size of 100 nm and single pores with a feature size of 30 nm in a silicon membrane are successfully fabricated at low cost using this method. This study paves the way towards the controllable, large-scale production of arrays of nanopores with desired size.