VLSI Implementation of a High Speed Multiplier Using on the Fly Conversion Technique

Abstract

An On the Fly Conversion Technique included array multiplier with optimum design. A multiplier loaded with N-Bit results to produce 2N bit partial products. The discermentation of bits will be as (2N) -(N/2) in addition with N/2 Bits. The Engineering of the bits differed with each other depending on the positions in their structure. This paper is considered in implementing an array multiplier put in effect using On the Fly Conversion Technique staked with Hybrid Full Adders abates the time delay. Instead of using a truncation or addition approach, the array multiplier described in this paper is constructed and implemented using a standard array multiplier scheme. The OTFC Logic Is used to boost Carry-Propagation at the final stage of Multiplication.To incorporate the MSB bits in parallel with the LSB bits, all of the final carry outputs were added into the OFTC circuit to get the result in less time. This work leads to achieve the sustainable development goals in the industry, innovation and Infrastructure.