High Quality Silicon Cap Layer for 28nm and Beyond PMOS Processes
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Published:2013-03-15
Issue:9
Volume:50
Page:419-424
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ISSN:1938-5862
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Container-title:ECS Transactions
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language:
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Short-container-title:ECS Trans.
Author:
Liao Chin I.,Hsuan Teng Chun,Chien Chin Cheng,Chan Michael,Yang Chan Lon,Wu J. Y.,Ramachandran Balasubramanian
Abstract
High quality embedded SiGe film with [Ge] concentration > 35% with Epitaxial grown Silicon (Si) cap layer has been demonstrated on a state-of-the-art 28nm logic flow. Si cap layer is a significant benefit to SiGe device for p-MOSFET contact resistance improvement but adversely affects the SiGe film strain relaxation especially for the high concentration [Ge] (> 35%). High quality, relaxation free SiGe film, with surface roughness improved from 4.21 to 0.65nm and 30% device contact resistance reduction are characterized in this work.
Publisher
The Electrochemical Society