A Vertically Integrated Capacitorless DRAM Cell

Abstract

A capacitorless cell with only 2 terminals is presented for high-density dynamic random access memory applications. Experiments and calibrated simulations were conducted, which prove that this memory cell has high operation speed (ns level), large read current margin (a read current ratio of 104), low process variation, good thermal reliability and available retention time (190ms). Furthermore, the memory cell is compatible with CMOS technology and free of cyclic endurance problem induced by hot-carrier injection due to the gateless structure.