Simulation and Experimental Study on Multilayer Double-Patterning Processes

Abstract

The imaging constraints imposed by the optics of current lithographic tools now require double-patterning (DP) processes. As lithography pushes past 32-nm resolution, the need to optimize material stacks, including resist, bottom anti-reflective coating (BARC), and substrate has never been greater for IC manufacturers. With thinner resists, DP, dual BARCs, and tri- and quad-layer schemes in the 193-nm immersion technology, the potential combinations are almost endless. Many approaches to DP have been devised, of which most have been designed to reduce the number of process steps. In this paper, we model several DP processes using our simulation software. Reflectivity control and resist profile optimization was maintained in the simulations using organic BARCs and spin-on multilayer stacks consisting of a silicon hardmask on top of a carbon underlayer. DP lithography results of these optimized tri- and quad-layer schemes are presented.