Surface Generation-Recombination Processes of Gate and STI Oxide Interfaces Responsible For Junction Leakage on SOI

Abstract

Carrier generation-recombination at the top, corner and trench surfaces of silicon-on-insulator (SOI) diode bodies have been studied using the standard gated-diode methodology and new test structures with independent trench-side gates. The influences of top or trench gate voltage, temperature and junction bias have been elucidated. Four distinct diode current peaks are observed during top-gate voltage sweeps. Qualitative analysis has assigned these peaks to surface recombination at the different surface areas of SOI bodies. The coexistence of multiple recombination current peaks might be related to silicon faceting at top trench corners. During top-gate voltage sweeps, STI-gate voltage causes a larger recombination current peak shift for interface traps at the SOI trench corners and walls than those at top SOI interface. A new model involving an oxide trap within the STI oxide has been proposed to interpret the random telegraphic signal (RTS) noise of a gated-diode at high carrier injection and temperature.