(Invited) “Small Size” Effects in Si-Based Epitaxies for Advanced CMOS Technologies

Abstract

Most of the Small Size Effects that take place in epitaxies used in advanced CMOS are reviewed. The most common one is the faceting that is a consequence of different deposition kinetics of the dense crystal planes. On the other hand, when considering small areas, the deposition rate is not a constant and the effective thickness depends on the pattern size and orientation. Thus, the concepts of “time-nonlinear kinetics” or “anisotropic loading effect” have been proposed. These epitaxies are also very sensitive to temperature. Thermal rounding takes place at temperatures as low as 600-625°C. Moreover, with higher thermal budgets, surface energy is capable, as a function of boundary conditions, to create instabilities such as Plateau-Rayleight ones or on the contrary to stabilize the Stranski-Krastanov ones. Finally, the importance of these mechanisms is illustrated in two CMOS applications: thermal rounding and anisotropic loading in SiGe channels and faceting in elevated sources/drains.