Author:
Yoshimoto Kazuhisa,Omura Y.,Wakabayashi Hitoshi
Abstract
This paper describes an impact of silicide layout in the S/D region on parasitic resistance of the multiple-fin triple-gate (TG) SOI MOSFET. For devices with narrow S/D region, it is demonstrated that P-shape layout with a thin silicide film results in the lowest parasitic resistance. On the other hand, for devices with wide S/D region, it is shown that a deep 'localized-silicide' layout results in the lowest parasitic resistance. The silicide/Si contact area should be as large as possible. It is also strongly suggested that a new technique is needed to reduce the parasitic resistance in sub-10-nm channel TG SOI MOSFET's.
Publisher
The Electrochemical Society
Cited by
2 articles.
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