(Invited) Interface and Border Traps in Ge pMOSFETs
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Published:2013-03-15
Issue:5
Volume:50
Page:189-203
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ISSN:1938-5862
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Container-title:ECS Transactions
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language:
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Short-container-title:ECS Trans.
Author:
Fleetwood Dan M,Simoen Eddy,Francis Sarah A.,Zhang C. X.,Arora Rajan,Zhang Enxia,Schrimpf Ron D.,Galloway Ken F.,Mitard Jerome,Claeys C.
Abstract
We have evaluated the effects of device processing and total-ionizing-dose (TID) radiation exposure on interface and border traps in Ge pMOSFETs. The defect density of these devices before and after TID irradiation is particularly sensitive to the number of Si monolayers at the substrate-to-dielectric interface and the halo doping conditions. These differences are reflected in the on-to-off current ratios, oxide- and interface-trap charge densities, and low-frequency noise exhibited by the devices. Lower halo implant doses are preferred over higher doses. An increase in the number of Si monolayers from five to eight improves the on-to-off current ratios and radiation response. The best overall performance in a radiation environment is observed for a process with eight Si overlayers and relatively low halo implant dose.
Publisher
The Electrochemical Society