Analysis of the Hysteresis Behavior in Poly-Si TFTs Using On-the-Fly Measurement

Abstract

The hysteresis behavior in p-type poly-Si TFTs causes malfunctions in analog circuits. To analyze the hysteresis, we adopted the On-the-Fly measurement that was used in the analyses of the negative bias temperature instability of Si LSIs. We modified the measurement for poly-Si TFTs and monitored the hole trapping from the fully detrapped states in order to quantitatively evaluate the hysteresis. A TFT annealed at 550oC had smaller trapping than a TFT annealed at 490oC due to fewer Si-OH bonds.