Physical Modeling of Layout-Dependent Transistor Performance

Abstract

Design for Manufacturability (DFM) is a phrase that often accompanies discussion of layout optimization for lithography process effects, particularly Optical Proximity Correction (OPC). In an environment where process technology and circuit design are developed together, many other process-layout co-optimization strategies can be investigated. In this paper we discuss physical modeling to enable co-optimization strategies from a device performance point of view by examining layout-induced variation in front-end manufacturing processes used to engineer transistor strain and dopant diffusion/activation.