Dielectric Breakdown Characteristics of Stacked High-k Dielectrics

Abstract

Dielectric breakdown characteristics of high-k dielectric have been intensively studied to develop a lifetime extrapolation model for device with metal/high-k gate stacks. Majority of prior works treated the high-k dielectric as a single layer dielectric like thermally grown SiO2 while the actual structure of high-k dielectric consists of two layers (high-k layer stacked on interfacial SiO2 like interfacial layer). And, the results of reliability test were interpreted using the model developed for SiO2. In the previous works, the potential limit of such approach has been pointed out; 1) severe electric field distortion due to transient charging in high-k dielectric during the stress, 2) excessive electrical stress applied to the interfacial layer. Thus, it was suggested that the extrapolation method using high field stress may not be correct for high-k dielectric. In this paper, several breakdown models suggested for high-k dielectric will be reviewed and compared to provide a comprehensive understanding on the current knowledge and challenges in this area.