Modeling of NPN-SiGe-HBT Electrical Performance Improvement through Employing Si3N4 Strain in the Collector Region

Abstract

A new NPN-SiGe-HBT device architecture utilizing a Si3N4 strain layer is proposed. The impact of introducing a Si3N4 strain layer in the collector region on the device's electrical properties and frequency characteristics has been studied using TCAD modeling. An approximately, 8% of improvement in fT, and 5% of improvement in fMAX have been achieved in the new NPN-SiGe-HBT device's architecture in comparison with an equivalent standard conventional NPN-SiGe-HBT device. Despite of the very small decrease in the breakdown voltage BVCEO value (1%─4%), the fT×BVCE0 product enhancement is about 6% by means of strain engineering.