High Precision Defect Inspection & Binning

Abstract

Wafer inspection and defect classification have been traditionally done in Fab solely using wafer level data. For processes as 45 nm and beyond, device performance has become very sensitive to process variations that include litho conditions and process-induced pattern fidelity. For example a slight mismatch in process chamber can have a drastic impact to yield. Also evaluation of OPC treatment on wafer is becoming more difficult when subtle pattern failures can be hidden in high volume of defect data. Certain defect type such as incomplete contact hole cannot be detected before etch and the occurrences can be intermittent, making it virtually impossible to detect them using random sampling [1]. In addition, Foundry Fabs need to meet the challenge of fast device characterization and quick ramp. Design-Aware inspection delivers new capability that allows Fabs to characterize device and process with higher dimension that were not possible before using the traditional approaches.