Impact of Dynamic Body Floating effect on Low-Energy Operation of XCT-SOI CMOS Devices with Aim of Sub-20-nm Regime

Abstract

This paper considers the dynamic and standby power dissipation characteristics of the scaled XCT-SOI MOSFET. Here, first, we analyze the low-energy operation of XCT-SOI CMOS circuits; the model proposed here strongly suggests that the ‘source potential floating effect (SPFE)’ substantially reduces the operation power consumption. Great advantages of the design methodology are also elucidated. In addition, this study addresses the reality of sub-20-nm-long gate XCT devices and a scaling scheme to suppress the standby power consumption for future low-energy applications.