Effect of Substrate Type on CoSi2 Formation in Rapid Thermal Annealing

Abstract

Annealing process optimization was performed to achieve low resistivity CoSi2 contacts used in different locations (word line, source, drain and gate regions) of advanced memory devices with various types of Si. The effect of Si type and annealing time on the resulting resistivity of the CoSi2 was investigated over a wide range of annealing temperatures (350 ~ 900oC) and times (60 ~ 300s) using a single wafer furnace-based (hot wall) rapid thermal annealing (RTA) system. The properties (conduction type, dopant, stacking structure and crystallinity) of the Si substrate contacting the Co film had a significant effect on the resulting CoSi2 formation temperature and contact resistance. In general, the CoSi2 formation temperature was reduced with the increase of RTA time. Significant differences in CoSi2 formation temperature was observed from different types of Si. The CoSi2 formation temperature for the source/drain (S/D) of P-type transistors was found to be the lowest. The CoSi2 formation temperature for poly Si, used in cells, was found to be the highest and was the limiting factor in RTA temperature reduction efforts.