Heterogeneous Chip Integration into Silicon Templates by Through-Wafer Copper Electroplating

Abstract

This work presents a strategy to enable heterogeneous integration by using electroplated copper as an embedding material to mechanically secure disparate electronic chips within a silicon template wafer. Manual placement of chips into template sockets yielded positional accuracy with <40 μm offset. Temporary facedown attachment of template and chips to a backing surface was utilized to achieve surface planarity with <10 μm topography. The surface of the resulting embedded wafer would be suitable for post-processing to realize interconnects.