Materials and Process Integration Issues in Metal Gate/High-k Stacks and Their Dependence on Device Performance
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Published:2007-09-28
Issue:4
Volume:11
Page:265-274
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ISSN:1938-5862
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Container-title:ECS Transactions
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language:
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Short-container-title:ECS Trans.
Author:
Callegari Alessandro,Babich Katherina,Zafar Sufi,Narayanan Vijay,Ando Takashi,Batson Philip E.
Abstract
Electron mobility, work function instabilities and re-growth of the thin SiO2 interfacial layer are main concerns for integrating metal/high-k stacks in high performance CMOS. High electron mobility has been obtained with both high (T~1000oC) and low (T~400oC) temperature processing but still the exact mechanism of the metal interaction with the gate stack is not fully understood. Threshold voltage control is also an open issue since metal/high-k stacks exhibit mid-gap work functions after high temperature annealing. Fixes have been proposed which require the introduction of positive (negative) charges near the Si/SiO2 interface to produce devices operating at the Si band edges.
Publisher
The Electrochemical Society
Cited by
1 articles.
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