Electrical Isolation of Dislocations in Ge Layers on Si(001) Substrates through CMOS Compatible Suspended Structures

Abstract

Suspended crystalline Ge semiconductor structures are created on a Si(001) substrate by a combination of epitaxial growth and simple patterning from the front surface using anisotropic underetching. Geometric definition of the surface Ge layer gives access to a range of planes to either retain or etch the underlying Si. The structures are aligned to avoid etch resistive planes in making the suspended regions and to take advantage of these planes to support the structures. The technique is demonstrated by forming suspended microwires, spiderwebs and Van-der Pauw cross structures. We finally report on the low temperature electrical isolation of the undoped Ge layers. This novel isolation method increases the 10{degree sign}K Ge resistivity to 280 Ω-cm, over two orders of magnitude above that of a bulk Ge on Si(001) layer, by removing material containing the underlying misfit dislocation network that otherwise provides the main source of electrical conduction.