Optimization of M1 to Contact Connection in Sub-40nm Node

Abstract

This paper presents integration challenges associated with M1 to CT connection in Ultra low-k (ULK) Back-End-Of-Line (BEOL) interconnects for 40nm node and beyond. In advance IC fabrication, porous dielectric materials, such as BDII (related dielectric constant k about 2.5), are commonly used as insulator in copper interconnects for RC delay reduction. But the material of inter-dielectric layer is still high density SiO2-based. Hence, the difference in materials of PMD and IMD would potentially induce mismatch of physical properties of the two types of dielectric and cause deterioration of M1 to Contact connection, which would further impact product yield by contact open or other issues. Cross section pictures of failing M1 to CT connection were exhibited with a special spacer profile and investigated to illustrate the phenomenon. Solutions were proposed, through optimization of Etch, Wet clean and CMP to improve process window. Layout optimization is also suggested as OPC and DFM solution for related layers. Some of the solutions were examined by experiments with 40nm BEOL test masks. Results of physical and electric characterization were presented and discussed.