Use of Polymer Liners for 3D-WLP TSVs: Process, Reliability and Cost

Abstract

Imec has developed 3D-WLP TSVs for the last 3 years using either CVD deposited or spin-on applied dielectric polymers as liner isolation. Three types of TSVs in either 100 or 50µm thick Si wafers are fabricated based on thinning first, via last approach where 3D interconnects are implemented on the backside of thinned IC fabricated device wafers. A 3-mask process sequence is implemented for fabrication of all TSV types, however, the process flow and the Si thickness are different for each one of them. All processes employed in the fabrication of the TSVs are performed at low temperature (<200°C) for post CMOS compatibility. The test vehicle used to develop the TSV technologies includes via daisy chains of various lengths connecting different number of vias to determine the TSV resistance and yield. We summarize in this paper, the key aspects of the three types of TSVs in terms of the fabrication, electrical characterization, and reliability; and we present the cost comparison of these TSVs.