Advanced Design Methodology of High-Performance Sub-100-nm-Channel GAA MOSFET-Reference-Cited by-同舟云学术

Advanced Design Methodology of High-Performance Sub-100-nm-Channel GAA MOSFET

Published:2009-05-15 Issue:4 Volume:19 Page:121-126
ISSN:1938-5862
Container-title:ECS Transactions
language:
Short-container-title:ECS Trans.

Author:

Nakano Shunsuke,Hayashi Osanori,Omura Yasuhisa,Yamakawa Shinya,Wakabayashi Hitoshi

Abstract

This paper reconsiders the design methodology of the short-channel GAA SOI MOSFET and proposes an advanced concept to enhance its performance. The new ideas are based on gate field engineering and source and drain diffusion engineering. Validity of the proposal is demonstrated by device simulations

Publisher

The Electrochemical Society

Link

https://iopscience.iop.org/article/10.1149/1.3117399/pdf

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1. Impact of Local High-κ Insulator on Drivability and Standby Power of Gate-All-Around SOI MOSFET;MOS Devices for Low-Voltage and Low-Energy Applications;2016-12-02

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