Process Optimization for 20nm Planar Pmos Device

Abstract

In this paper, we studied metal gate and implant process for optimization 20nm planar PMOS logic device, including metal gate work function tuning and performance enhancement. The paper has checked in details the work function sensitivity to metal gate related processes and also showed the impact on PMOS device performance. If Al diffuses to PWF (PMOS work function) layer, long channel device sub-threshold voltage shifts higher and short channel device performance degrades obviously. Thick PMOS work function layer or add of Al diffuse barrier layer can avoid the issue. We also showed that PWF layer removal process (PMOS work function layer needs be removed at NMOS area) impacts on PMOS device parameters and the process window needs careful tuning. Implant optimization can obviously improve PMOS device performance with embed-SiGe source/drain.