Defect Engineering Considerations for Strained Silicon Substrates

Abstract

Defect-engineering parameters influence the electrical performance of p-n junctions in strained silicon (SSi) substrates. The thin SSi layers were deposited on thin Strain Relaxed SiGe Buffers (SRBs), whereby strain relaxation is achieved by implementing a thin C-doped SiGe layer. Processing variables studied are the depth dC of this layer and the carbon concentration, determining the threading dislocations (TDs) density. As references, step-graded SRB material and standard Czochralski silicon was used. Combined current-voltage and capacitance-voltage measurements indicate that within the range studied (2-3x105 to 1-2x107 cm-2), the TDD has the strongest impact on the reverse current density and generation lifetime. Additional leakage current is created by defects associated with the carbon-rich layer, when present in the junction depletion region. The electrical activity of the TDs also depends on the well doping type (n- or p). The largest activity is observed in n+/p junctions, which are technologically the more relevant ones.