Ultra Low Power 6T SRAM Cell Designed on 65nm Low Power Technology Platform Suitable for High Temperature Applications

Abstract

Cell leakage (Istby) reduction of ultra low power (ULP) SRAM with conventional 6T configuration on 65nm low power (LP) technology platform is studied in the paper. Istby components are analyzed and optimized for the leakage reduction by adopting no sleep transistor or other leakage suppression schemes. Gate oxide of cell transistor is grown thicker compared to 65nm LP process to fully suppress the gate oxide leakage contribution. Sub-threshold leakage of the cell transistors are much decreased to lower down both the total Istby and its temperature sensitivity. The 16M ULP SRAM featuring a 0.525um2 bit cell size with the proposed technique shows Istby as low as 1.2pA/bit at 1.2V under room temperature and 3.1pA/bit at 85℃. The voltage data retention (VDR) of the ULP SRAM is shown to be 0.7V indicating the feasibility of Istby further reduction by applying low Vdd under stand by mode. Moreover, the ULP process is fully compatible with logic process flow, by adopting several more masks, the above mentioned SRAM can be embedded into standard CMOS flow easily.