A Software Based Many-Core Architecture Simulator

Abstract

As technology continuously advances, engineers are constantly faced with challenges that require numerous computational designs and implementations that, usually, go beyond practical feasibility, considering the available resources at hand. An area that might be considered for dealing with these problems relates to the use of many-core architectures for parallel processing. This type of architecture can be extremely efficient for intensive computational tasks and has the power to operate with low energy and low clock frequencies; however scalability issues attached to the process can significantly affect its design. This paper presents the technicalities involved in developing a scalable many-core software-based simulator named SImulator for Many-Cores (SIMC) that includes features such as package routing and efficient inter-process communication. It is intended as a project goal that SIMC becomes a useful software package that allows students with interests in simulating many-core based hardware projects as software systems. It is also intended that by practicing with SIMC on a diverse set of problems, students can acquire experience in analyzing metrics, such as speed and latency, among others that are commonly used in this sort of scenario. The type of practice provided by SIMC promotes a way of fixing the several hardware related concepts involved as well as to enlarge and refine student´s skills in programming. For the case study described in this paper, the validation of SIMC has been carried out by means of solving a relatively trivial problem i.e., that of the execution of simple morphological filters, where the allocation of tasks can be optimized for improving either the execution speed or latency. SIMC allows a direct comparison of values of both metrics, as well as a quantitative evaluation of the implemented network as a whole.