Wide Bandgap SiC-Based Oxide Thickness Optimization by Computation and Simulation using Enhanced Electron Mobility with Regulated Gate Voltage Technique for High-Power 4H-SiC MOSFET

Abstract

This work analyzed the interactions between gate oxide thickness (Tox), voltage dependence, and electron mobility (E-mobility) in the inversion layer, which controls the electron movement properties of 4H-SiC/SiO2. This paper also presents a calculation of gate oxide thickness in correlation with gate voltage mainly for high-voltage applications. The results of this work revealed that at low resistance, E-mobility increases with gate voltage and oxide thickness, which saturates at the point of value. Coulomb scattering and surface phonons at the inversion region of SiC MOSFETs are regarded as the two primary factors that limit E-mobility in these devices. In addition, the high interface trap density (Dit) causes a decrease in E-mobility. The findings from this study confirmed that the computed values of oxide thickness and simulation-based oxide thickness with regulated gate voltages have the least variation below 1%, asserting experimental and theoretical outcomes about the role of oxide thickness and electron movement at the 4H-SiC/SiO2 interfaces. These results indicate that understanding the E-mobility effect on oxide thickness in the SiC MOSFET inversion layer according to gate voltage is important, particularly in achieving an optimal 4H-SiC/SiO2 interface for high-power applications.