Improving LUT count of FPGA-based sequential blocks-Reference-Cited by-同舟云学术

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Improving LUT count of FPGA-based sequential blocks

Published:2021-03-02 Issue: Volume: Page:136728-136728
ISSN:2300-1917
Container-title:Bulletin of the Polish Academy of Sciences Technical Sciences
language:pl
Short-container-title:

Author:

Barkalov Alexander¹²^ORCID,Titarenko Larysa¹³^ORCID,Mazurkiewicz Małgorzata¹^ORCID,Krzywicki Kazimierz⁴^ORCID

Affiliation:

1. University of Zielona Góra, ul. Licealna 9, 65-417 Zielona Góra, Poland

2. Vasyl’ Stus Dohetsk National University, 21, 600-richya str., Vinytsia, 21021, Ukraine

3. Kharkiv National University of Radio Electronics, Nauky avenye, 14, 6166, Kharkiv, Ukraine

4. The Jacob of Paradies University, ul. Teatralna 25, 66-400 Gorzów Wielkopolski, Poland

Publisher

Polish Academy of Sciences Chancellery

Subject

Artificial Intelligence,Computer Networks and Communications,General Engineering,Information Systems,Atomic and Molecular Physics, and Optics

Link

https://journals.pan.pl/Content/119412/PDF/29_01817_Bpast.No.69(2)_26.04.21_K1_G_TeX_OK.pdf

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Structural Decomposition in FSM Design: Roots, Evolution, Current State—A Review;Electronics;2021-05-14

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