Low‐clock‐speed time‐interleaved architecture for a polar delta–sigma modulator transmitter-Reference-Cited by-同舟云学术

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Low‐clock‐speed time‐interleaved architecture for a polar delta–sigma modulator transmitter

Published:2022-07-17 Issue:1 Volume:45 Page:150-162
ISSN:1225-6463
Container-title:ETRI Journal
language:en
Short-container-title:ETRI Journal

Author:

Erfani Majd Nasser¹^ORCID,Fani Rezvan¹

Affiliation:

1. Department of Electrical Engineering, Shohadaye Hoveizeh Campus of Technology Shahid Chamran University of Ahvaz Dasht‐e Azadegan Khuzestan Iran

Publisher

Wiley

Subject

Electrical and Electronic Engineering,General Computer Science,Electronic, Optical and Magnetic Materials

Link

https://onlinelibrary.wiley.com/doi/pdf/10.4218/etrij.2021-0443

Reference28 articles.

1. Study the effect of PAPR on wideband cognitive OFDM radio networks

2. RF and Microwave Transmitter Design

3. B. T.Thiel A.Özmert J.Guan andR.Negra Lowpass delta sigma modulator with digital upconversion for switching mode power amplifiers (IEEE MTT‐S International Microwaves Symposium Baltimore MD USA) June2011 pp.5–10.

4. Sigma–delta digital drive signals for switch-mode power amplifiers

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