Performance and analysis of different adder topologies-Reference-Cited by-同舟云学术

Performance and analysis of different adder topologies

Published:2024 Issue:3 Volume:14 Page:31
ISSN:2229-7286
Container-title:i-manager’s Journal on Electronics Engineering
language:en
Short-container-title:JELE

Author:

Rashmi B. K.¹,Rohith J.¹,Shreya Suresh Mudaladavar¹,Supreet Hosageri¹,Mahantesh P. Mattada¹

Affiliation:

1. PES Institute of Technology and Management

Abstract

This paper gives an overview of area, power, delay for four different 64-bit adders. The design metrics in VLSI are low area and delay alongside low power designs. Adder is one of the necessary components of almost every kind of digital and high- performance systems such as FIR filters, digital signal processors and microprocessors etc. Different types of adders are carry tree adder, carry save adder, carry look ahead adder and carry select adder. In this work we have designed, simulated and synthesized these adder topologies and compared the results in cadence tool.

Publisher

i-manager Publications

Reference14 articles.

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