A comparative analysis of different current mirror techniques in 65nm technology

Abstract

The Current Mirror (CM) technique is widely used in mixed-mode and analog integrated circuits for tasks such as current amplification, biasing, and active loading. The overall effectiveness of these circuits relies heavily on their efficient designs. Current mirrors are primarily employed to accurately replicate currents in a circuit, offering high stability, simplicity, and scalability. They have become indispensable building blocks in analog and mixed-signal circuits, with their significance growing along with the demand for high-performance and low-power designs. Numerous techniques have been proposed to improve the performance metrics of current mirrors, including accuracy, input resistance, output resistance, and bandwidth. This study compares the advantages and disadvantages of these different current mirror techniques on a unified platform. It includes a comprehensive analysis of various contemporary mirror topologies, and classifies them based on their distinct characteristics. The performances of different current mirrors, including the basic CM, Wilson CM, cascode CM, and folded cascode CM circuits, were thoroughly examined in this analysis. The objective of this study is to select an appropriate current mirror for specific applications. The circuits considered in this study accurately mirror a current of 100 µA with a ±2% error using the Cadence Virtuoso software and UMC 65 nm technology. Process, Voltage, and Temperature (PVT) analysis, along with Monte Carlo simulations, were conducted under similar conditions using a supply voltage of 1.2V to ensure a fair comparison across the various current mirror approaches.